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Macros | |
#define | AMREX_GPU_LAUNCH_HOST_DEVICE_LAMBDA_RANGE(TN, TI, block) |
#define | AMREX_GPU_LAUNCH_HOST_DEVICE_LAMBDA_RANGE_2(TN1, TI1, block1, TN2, TI2, block2) |
#define | AMREX_GPU_LAUNCH_HOST_DEVICE_LAMBDA_RANGE_3(TN1, TI1, block1, TN2, TI2, block2, TN3, TI3, block3) |
#define | AMREX_GPU_LAUNCH_DEVICE_LAMBDA_RANGE(TN, TI, block) |
#define | AMREX_GPU_LAUNCH_DEVICE_LAMBDA_RANGE_2(TN1, TI1, block1, TN2, TI2, block2) |
#define | AMREX_GPU_LAUNCH_DEVICE_LAMBDA_RANGE_3(TN1, TI1, block1, TN2, TI2, block2, TN3, TI3, block3) |
#define | AMREX_HOST_DEVICE_FOR_1D(n, i, block) |
#define | AMREX_HOST_DEVICE_PARALLEL_FOR_1D(n, i, block) |
#define | AMREX_FOR_1D(n, i, block) |
#define | AMREX_PARALLEL_FOR_1D(n, i, block) |
#define | AMREX_HOST_DEVICE_FOR_3D(box, i, j, k, block) |
#define | AMREX_HOST_DEVICE_PARALLEL_FOR_3D(box, i, j, k, block) |
#define | AMREX_FOR_3D(box, i, j, k, block) |
#define | AMREX_PARALLEL_FOR_3D(box, i, j, k, block) |
#define | AMREX_HOST_DEVICE_FOR_4D(box, ncomp, i, j, k, n, block) |
#define | AMREX_HOST_DEVICE_PARALLEL_FOR_4D(box, ncomp, i, j, k, n, block) |
#define | AMREX_FOR_4D(box, ncomp, i, j, k, n, block) |
#define | AMREX_PARALLEL_FOR_4D(box, ncomp, i, j, k, n, block) |
#define AMREX_FOR_1D | ( | n, | |
i, | |||
block | |||
) |
#define AMREX_FOR_3D | ( | box, | |
i, | |||
j, | |||
k, | |||
block | |||
) |
#define AMREX_FOR_4D | ( | box, | |
ncomp, | |||
i, | |||
j, | |||
k, | |||
n, | |||
block | |||
) |
#define AMREX_GPU_LAUNCH_DEVICE_LAMBDA_RANGE | ( | TN, | |
TI, | |||
block | |||
) |
#define AMREX_GPU_LAUNCH_DEVICE_LAMBDA_RANGE_2 | ( | TN1, | |
TI1, | |||
block1, | |||
TN2, | |||
TI2, | |||
block2 | |||
) |
#define AMREX_GPU_LAUNCH_DEVICE_LAMBDA_RANGE_3 | ( | TN1, | |
TI1, | |||
block1, | |||
TN2, | |||
TI2, | |||
block2, | |||
TN3, | |||
TI3, | |||
block3 | |||
) |
#define AMREX_GPU_LAUNCH_HOST_DEVICE_LAMBDA_RANGE | ( | TN, | |
TI, | |||
block | |||
) |
#define AMREX_GPU_LAUNCH_HOST_DEVICE_LAMBDA_RANGE_2 | ( | TN1, | |
TI1, | |||
block1, | |||
TN2, | |||
TI2, | |||
block2 | |||
) |
#define AMREX_GPU_LAUNCH_HOST_DEVICE_LAMBDA_RANGE_3 | ( | TN1, | |
TI1, | |||
block1, | |||
TN2, | |||
TI2, | |||
block2, | |||
TN3, | |||
TI3, | |||
block3 | |||
) |
#define AMREX_HOST_DEVICE_FOR_1D | ( | n, | |
i, | |||
block | |||
) |
#define AMREX_HOST_DEVICE_FOR_3D | ( | box, | |
i, | |||
j, | |||
k, | |||
block | |||
) |
#define AMREX_HOST_DEVICE_FOR_4D | ( | box, | |
ncomp, | |||
i, | |||
j, | |||
k, | |||
n, | |||
block | |||
) |
#define AMREX_HOST_DEVICE_PARALLEL_FOR_1D | ( | n, | |
i, | |||
block | |||
) |
#define AMREX_HOST_DEVICE_PARALLEL_FOR_3D | ( | box, | |
i, | |||
j, | |||
k, | |||
block | |||
) |
#define AMREX_HOST_DEVICE_PARALLEL_FOR_4D | ( | box, | |
ncomp, | |||
i, | |||
j, | |||
k, | |||
n, | |||
block | |||
) |
#define AMREX_PARALLEL_FOR_1D | ( | n, | |
i, | |||
block | |||
) |
#define AMREX_PARALLEL_FOR_3D | ( | box, | |
i, | |||
j, | |||
k, | |||
block | |||
) |
#define AMREX_PARALLEL_FOR_4D | ( | box, | |
ncomp, | |||
i, | |||
j, | |||
k, | |||
n, | |||
block | |||
) |